Apple’s Server Chip May Rely on Intel EMIB Packaging as TSMC CoWoS Capacity Tightens
Apple’s push into custom server silicon appears to be entering a new phase, with fresh reports suggesting that Intel could play a key role in the back end of Apple’s AI chip strategy. While Apple is still expected to rely on TSMC for leading edge fabrication, new information indicates that Intel’s advanced packaging technologies may be brought in to offset growing capacity constraints at TSMC.
According to an industry note highlighted by Jukanlosreve, Apple’s bespoke AI server chips developed in collaboration with Broadcom could adopt Intel’s EMIB packaging technology as early as 2028. The shift is reportedly being considered due to the severe undersupply of TSMC’s CoWoS packaging capacity, which has become one of the biggest bottlenecks in the AI hardware ecosystem.
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TSMC’s Chip on Wafer on Substrate technology is a cornerstone of modern high performance silicon design. CoWoS enables the tight integration of multiple dies such as CPUs GPUs and High Bandwidth Memory on a silicon interposer, delivering the bandwidth and efficiency required by advanced AI workloads. However demand from hyperscalers and AI accelerators has stretched CoWoS capacity to its limits, creating delays and forcing customers to explore alternatives.
A recent research note from GF Securities Hong Kong reinforces this view, stating that Intel is positioned to benefit directly from the CoWoS undersupply at TSMC. The report reiterates that Apple is actively evaluating Intel’s 18A P process for future products, particularly lower tier M series chips targeted for release around 2027. Apple is said to have already signed a non disclosure agreement with Intel and obtained process design kit samples for early evaluation of the 18A P node.
More notably, GF Securities suggests that Apple and Broadcom’s custom ASICs will transition to Intel’s EMIB packaging in 2028. EMIB or Embedded Multi die Interconnect Bridge allows multiple chiplets to be connected within a single package without the need for a full silicon interposer, offering a scalable and potentially more available alternative to CoWoS for complex designs.
This development aligns with earlier reports from Spring 2024, which revealed that Apple and Broadcom were jointly developing Apple’s first dedicated AI server chip under the internal codename Baltra. At the time shipments were expected to begin in 2027. The latest assessment from the Hong Kong based brokerage firm now suggests that volume availability may slip to 2028, likely due to ongoing constraints in advanced packaging and supply chain readiness.
Intel’s role could expand further. GF Securities has previously stated that Apple may adopt Intel’s 18A P process for non Pro iPhone chips as early as 2028. The 18A P node is particularly notable as it is Intel’s first process to support Foveros Direct three dimensional hybrid bonding, enabling high density chiplet stacking through through silicon vias. This capability could prove attractive for future Apple designs that prioritize power efficiency and integration density.
These reports arrive as Intel prepares to establish a dedicated ASIC unit aimed at helping external customers design and tape out custom silicon tailored to specific workloads. If Apple does move forward with Intel for both packaging and potentially fabrication, it would mark a significant shift in the competitive dynamics between Intel and TSMC at the high end of the semiconductor market.
While nothing has been officially confirmed by Apple Intel or Broadcom, the growing pressure on CoWoS capacity is forcing even the largest players to diversify their supply chains. For Apple, combining TSMC’s manufacturing leadership with Intel’s advanced packaging could offer a pragmatic path forward as AI infrastructure demand continues to surge.
Do you think Apple adopting Intel EMIB packaging could signal a broader industry shift away from exclusive reliance on TSMC CoWoS for AI silicon? Share your thoughts below.
