AMD CoWoS Demand Could Quadruple in 2027 as Agentic AI Drives EPYC Venice
AMD could become one of the biggest drivers of TSMC advanced packaging growth in 2027 as demand for EPYC Venice processors and Instinct MI400 Series accelerators accelerates alongside the expansion of agentic AI infrastructure. According to estimates from Morgan Stanley, AMD could consume approximately 530,000 CoWoS wafers during 2027, compared with around 130,000 in 2026. That would represent growth of roughly 308% in a single year and increase AMD share of total CoWoS demand from approximately 9% to 20%.
The biggest contributor may surprisingly be CPUs rather than AI GPUs. Morgan Stanley estimates that CoWoS demand associated with AMD 6th Generation EPYC Venice processors could climb from around 50,000 wafers in 2026 to approximately 270,000 wafers in 2027. AMD has already placed EPYC 9006 Venice into production using TSMC 2 nm technology and is positioning the architecture directly around increasingly complex agentic AI infrastructure. The processors scale to as many as 256 Zen 6 cores and 512 threads per socket, with up to 16 channels of DDR5 memory, MRDIMM support reaching 12,800 MT/s and PCIe 6 connectivity.
$AMD | Baird's Tristan Gerra on 12 months his $1,250 PT🚨
— Mike (@MikeLongTerm) August 17, 2026
Baird analyst Tristan Gerra raised his 12-month price target on Advanced Micro Devices (@AMD ) to $1,250 from $625 while maintaining an Outperform (Buy) rating. This became the Street-high target at the time.
The upgrade… https://t.co/e5J8boeFJs pic.twitter.com/nMUyafccF6
Agentic AI is changing the balance inside the data center because accelerators are only one part of a much larger execution pipeline. Agents continuously interact with databases, APIs, storage, networking, security systems, applications and other services while GPUs perform the heavier AI computation. AMD argues that CPUs therefore become increasingly important for orchestration, scheduling, data preparation, control flow and maintaining accelerator utilization as the number of simultaneous agents increases. This strategy is already visible in EPYC Venice entering volume production on TSMC 2 nm, where AMD positioned the processor as a foundation for next generation AI infrastructure.
AMD is also consuming more advanced packaging through its accelerator roadmap. The Instinct MI455X uses the CDNA 5 architecture and a multi chiplet design, while AMD Helios integrates 72 MI455X accelerators with 18 EPYC Venice processors, Pensando networking and ROCm software. AMD has already secured large deployments with Microsoft, Meta, Anthropic and other AI customers, creating a much stronger commercial foundation for the MI400 generation than AMD had during earlier Instinct launches. Microsoft will begin receiving Helios systems during 2H 2026, while AMD says deployments will accelerate throughout 2027.
The packaging requirements are particularly significant because AMD increasingly relies on complex chiplet designs rather than monolithic processors. AMD has officially confirmed that its broader data center portfolio uses technologies including TSMC SoIC X and CoWoS L, while the company announced more than 10$ billion in Taiwan ecosystem investments in May to strengthen semiconductor manufacturing and advanced packaging capacity. These technologies allow AMD to combine compute dies, I/O silicon and high bandwidth memory within increasingly sophisticated packages, but they also make access to packaging capacity a critical production constraint.
NVIDIA is not expected to lose its position as TSMC largest CoWoS customer. Morgan Stanley estimates NVIDIA could consume around 1.2 million CoWoS wafers during 2027, representing approximately 57% growth from 2026. However, NVIDIA share of overall CoWoS demand could fall from around 53.4% in 2026 to 45.6% in 2027 because the entire market is expanding even faster. Total industry demand is estimated to reach approximately 2.7 million wafers in 2027, nearly 93% higher than 2026. In other words, AMD gaining share does not require NVIDIA demand to decline. Both companies can consume considerably more packaging while NVIDIA represents a smaller percentage of a much larger market.
That distinction is important because CoWoS remains one of the most critical bottlenecks in AI semiconductor manufacturing. TSMC continues expanding advanced packaging aggressively, with industry reports pointing toward monthly CoWoS capacity of at least 200,000 wafers during 2027. The company is also moving toward substantially larger package designs, while recent CoWoS production has reportedly reached yields above 98%. Even with that expansion, NVIDIA, AMD, Broadcom and custom accelerator developers are all increasing demand at the same time.
AMD momentum also aligns with a broader shift toward inference. Lisa Su recently said some of the company largest AI deployments are increasingly focused on inference rather than only training, while AMD has already started sampling MI450 hardware as inference demand expands. Agentic systems amplify that shift because they require continuous model execution alongside significant CPU activity, potentially allowing AMD to benefit from both accelerator demand and its already established EPYC server business.
AMD potentially quadrupling its CoWoS consumption is significant, but the most important part of the forecast is where that demand is coming from. The AI infrastructure race is expanding beyond GPUs. Agentic AI requires accelerators for inference, but it also creates enormous workloads around orchestration, databases, storage, networking, security and application execution. That gives high core count server CPUs a much larger role inside future AI factories.
NVIDIA should still remain the dominant CoWoS customer in absolute volume, so this is not a story about AMD replacing NVIDIA. It is a story about the advanced packaging market becoming much broader. If AMD reaches around 20% of total CoWoS demand while NVIDIA continues increasing its own consumption, TSMC faces an environment where several customers simultaneously need hundreds of thousands or even millions of advanced packages. Packaging capacity could therefore become just as strategically important as access to 2 nm and 3 nm wafers, HBM and server memory.
Could EPYC Venice and agentic AI turn server CPUs into one of AMD biggest growth opportunities, or will AI spending remain dominated by GPUs?
