Pat Gelsinger Calls HBM "Hideous" as DRAM Shortages Loom Into 2028
Former Intel CEO Pat Gelsinger has renewed his criticism of High Bandwidth Memory (HBM), describing the technology as fundamentally flawed despite its importance to modern AI accelerators. During a recent interview with a16z, Gelsinger highlighted limitations involving memory density, thermal efficiency, and physical bandwidth constraints. His comments arrive as Taiwanese memory manufacturer Nanya Technology warns that the ongoing DRAM shortage could extend into early 2028.
"HBM is a hideous memory. That's just the best one that we got."
— Quote by: Pat Gelsinger
Gelsinger argues that HBM introduces several architectural compromises despite delivering the enormous bandwidth required by AI workloads. Unlike conventional DDR memory, HBM stacks multiple DRAM dies vertically and connects them through Through Silicon Vias (TSVs), requiring advanced packaging technologies and extensive physical connections to the processor. According to SemiAnalysis, these manufacturing requirements reduce bit density within individual memory dies and create limitations around the available perimeter of a compute chip, commonly referred to as shoreline bandwidth.
Why Gelsinger Criticizes HBM
| Technical Limitation | Impact on HBM |
|---|---|
| Bit Density | TSVs occupy silicon area that could otherwise contain memory cells |
| Shoreline Bandwidth | Physical interface requirements limit how many HBM stacks can connect to a processor |
| Thermal Efficiency | Concentrated heat from GPUs and memory interfaces complicates cooling |
| Manufacturing | Advanced stacking and packaging increase complexity and production costs |
Thermal management is particularly challenging because HBM operates extremely close to powerful accelerators. A KAIST research study found that GPU heat transfer dominates memory thermal behavior below 30 W of HBM power consumption in its analyzed configuration, while heat generated by the HBM physical interface becomes the primary contributor above that threshold.
Gelsinger previously expressed similar concerns during the July 2026 RAISE Summit, describing HBM as a "lousy memory," as discussed by Vikram Sekar. His argument is not that HBM lacks value, but that the industry needs new memory architectures capable of overcoming its physical limitations.
Meanwhile, Nanya Technology's latest industry outlook suggests DRAM shortages could persist until early 2028 as AI infrastructure continues absorbing manufacturing capacity. Construction delays and longer semiconductor equipment delivery times are slowing production expansion, while approximately 50% to 70% of Nanya's business is already covered by long term supply agreements.
The company's Q3 2026 financial results reinforce the severity of current market conditions, with DRAM average selling prices increasing by more than 60% compared with the previous quarter. Nanya expects its new manufacturing facility to reach 30,000 wafer starts per month by the end of 2028, with further expansion planned through 2030.
These conditions also reflect the wider pressure on conventional DDR4 and DDR5 availability. HBM production consumes substantial semiconductor manufacturing resources, while growing demand for server memory further reduces the supply available to consumer and industrial markets.
Gelsinger's criticism highlights a contradiction in the current semiconductor industry. HBM is essential for modern AI computing, yet its manufacturing complexity and physical limitations make it increasingly difficult and expensive to scale.
The real concern extends beyond AI accelerators. With memory manufacturers prioritizing HBM and server DRAM, gaming PCs, graphics cards, laptops, and workstation systems are competing for increasingly constrained supplies of conventional memory.
HBM will remain critical in the near term, but its limitations create opportunities for alternative architectures, improved packaging, and technologies that bring memory closer to processing resources. Until those solutions mature and manufacturing capacity expands, the industry could continue facing higher costs and limited availability.
Do you believe HBM will remain the dominant memory technology for AI accelerators, or will its limitations eventually force the industry to adopt an entirely new architecture?
