Intel Breaks Ground on Santa Clara Mask Manufacturing Expansion

Intel has started construction on a major expansion of its Bowers Campus in Santa Clara, California, strengthening the domestic manufacturing infrastructure that supports the company’s advanced semiconductor process roadmap.

The June 30, 2026 groundbreaking ceremony included Intel Chief Executive Officer Lip Bu Tan, Intel Foundry Executive Vice President Naga Chandrasekaran, Intel Mask Operations Vice President Frank Abboud, James Chew from Intel Federal, and other engineering and manufacturing leaders. Images from the event were shared by Pushkar Ranade and Ashish Tuli, showing Intel leadership formally beginning construction at the Santa Clara site.

The approved project covers approximately 2.4 acres at 3065 Bowers Avenue and includes a new manufacturing building called BW2 with an attached central utility building called CUB2. Both structures will contain 3 floors and provide a combined area of 107,171 square feet, according to the official City of Santa Clara development listing. The utility building will provide the infrastructure required for the manufacturing equipment installed inside the new facility.

The project should not be interpreted as a conventional semiconductor wafer fabrication plant. Intel’s Bowers Campus is home to Intel Mask Operations, which designs and manufactures the photolithography masks used across the company’s global production network. These masks contain the detailed circuit patterns transferred onto semiconductor wafers during lithography and are essential for every advanced manufacturing process. Intel says the site produces masks used to manufacture hundreds of millions of chips across its worldwide factories.

Expanding mask production capacity in California gives Intel greater control over one of the most technically demanding parts of advanced process development. As transistor structures become smaller and chip designs become more complex, mask manufacturing requires increasingly precise patterning, inspection, defect control, and correction capabilities.

The facility is expected to support Intel’s future process technologies, including Intel 18A P and Intel 14A. Intel 18A P entered risk production in June 2026 and offers 9% higher performance at the same power or 18% lower power at the same performance compared with the original Intel 18A process. It also introduces improved thermal characteristics, lower resistance connections, additional transistor options, and design compatibility with existing Intel 18A intellectual property.

“We are fully committed to leading edge process innovation over the long term.”
— Naga Chandrasekaran

Our previous report on Intel 18A P entering risk production examined how Power Boost, RibbonFET transistors, and PowerVia backside power delivery could improve performance and efficiency while allowing customers to reuse existing Intel 18A design flows.

Intel 14A represents the company’s next major foundry generation and is being developed in closer collaboration with external customers. The process is expected to use second generation RibbonFET technology, PowerDirect backside power delivery, and High NA EUV lithography on selected layers. Intel has distributed early design kits to lead customers and says multiple companies have expressed interest in producing test chips.

The company is also building the wider software and design ecosystem needed to commercialize 14A. Intel and Cadence foundry is working together on process design kits, intellectual property, design technology optimization, and artificial intelligence assisted engineering tools. Intel recently reorganized its Foundry leadership to place greater operational focus on manufacturing execution. Naga Chandrasekaran now leads front end process development and manufacturing, including Intel 18A, Intel 14A, design enablement, and customer operations. Former SK hynix Chief Executive Officer Seok Hee Lee leads advanced packaging, system integration, back end development, and back end manufacturing. Intel says this structure is intended to improve speed, consistency, and predictability for customers.

The Santa Clara expansion also supports Intel’s broader strategy of maintaining semiconductor research, development, manufacturing, and advanced packaging capabilities inside the United States. The company has stated that Intel 18A and Intel 14A research, development, and wafer production will remain based in the country, supported by facilities in California, Oregon, Arizona, and New Mexico.

Intel is simultaneously investing in advanced packaging technologies including EMIB, Foveros, hybrid bonding, and glass substrates. The Bowers Campus project is smaller than Intel’s multibillion dollar wafer fabrication investments, but its strategic importance should not be underestimated. Advanced manufacturing depends on more than lithography machines and production capacity. Every new process requires precise masks, inspection systems, correction tools, design infrastructure, utilities, and engineering expertise.

Keeping mask development close to Intel’s headquarters and process engineering teams could reduce development cycles and strengthen coordination between design, lithography, manufacturing, and customer support. That becomes increasingly important as Intel attempts to prove that its Foundry roadmap can deliver predictable results for external customers.

The expansion also represents a practical commitment to United States semiconductor manufacturing. Intel is not only announcing future nodes or customer interest. It is investing in the physical infrastructure required to develop and manufacture the tools that make those processes possible.

The decisive challenge remains execution. New buildings and stronger technology specifications will only matter when Intel converts them into mature yields, competitive production costs, dependable delivery schedules, and major external customer products. The Santa Clara expansion provides another piece of that manufacturing foundation, but Intel 18A P and Intel 14A will ultimately be judged by commercial silicon.

Can Intel’s expanding United States manufacturing infrastructure help Foundry become a serious alternative to TSMC and Samsung for advanced chip production?