Empyrean Cuts Circuit Layout Time by 75% With Agentic AI

Chinese electronic design automation company Empyrean Technology says it has reduced the time required for a circuit layout task from 4 weeks to just 1 week by introducing Agentic AI into its EDA workflow, representing a 75% reduction for that particular design task.

Empyrean Chairman Liu Weiping disclosed the result during the 2026 International Integrated Circuit Innovation Expo in Shenzhen. According to reporting from South China Morning Post, the company applied an AI agent across its simulation and layout tools, allowing the system to handle parts of the design workflow with substantially less direct engineering intervention. The 75% figure refers specifically to the tested circuit layout workload rather than the complete process required to design, verify, and manufacture a semiconductor.

Empyrean is now developing a broader Agentic EDA platform intended to allow its own agents to interact with tools and agents created by partners. Liu sees the technology changing EDA from a workflow where engineers manually operate individual tools toward one where engineers provide higher level objectives and agents coordinate the required software underneath.

The company's 2026 interim report shows that this strategy already extends across several parts of its portfolio. Empyrean has introduced AI into process diagnosis, automated programming, physical verification, custom design, and display circuit development. Its PyAether agent can assist with API searches, information matching, and natural language code generation, while other AI systems are being used to filter false verification results and automate portions of physical design.

Empyrean is not alone in moving toward autonomous semiconductor development. Cadence says its ChipStack AI Super Agent can deliver up to 10 times higher productivity across areas including RTL development, testbench generation, verification planning, regression testing, and debugging. The company later demonstrated Level 5 autonomous workflows capable of reducing some RTL verification cycles from 5 weeks to less than 1 day.

Synopsys is pursuing a similar direction through AgentEngineer, reporting up to 50 times faster delivery of validated RTL in one autonomous verification workflow. Its work with AMD and Microsoft has also produced autonomous EDA workflows that showed up to a 40% reduction in development cycle time during initial testing.

The broader change is already becoming visible across semiconductor development. Samsung has begun applying AI coding tools to chip engineering, as covered in our report on Claude Code expanding into semiconductor design, while Intel and Cadence are using AI assisted EDA technologies around future manufacturing platforms including Intel 14A.

For China, the technology also carries strategic importance. Empyrean is one of the country's most prominent domestic EDA developers, and its expanding AI portfolio provides another route for improving semiconductor design productivity while China continues investing heavily in domestic chip design and manufacturing infrastructure.

Agentic AI could become one of the biggest changes to semiconductor design since EDA itself became central to modern chip development.

The important detail is not that AI designed an entire chip 75% faster. It did not. Empyrean demonstrated a 75% reduction in the time required for one circuit layout task, which is still meaningful because modern semiconductor projects contain enormous numbers of repetitive design, simulation, verification, and optimization steps.

The larger opportunity comes when specialized agents can coordinate many of those tasks while engineers retain control of architecture and final signoff. Cadence, Synopsys, Empyrean, and chip companies are all moving toward that model, suggesting that the next semiconductor productivity race may be fought as much through AI assisted engineering as through faster manufacturing nodes.

Would you trust Agentic AI to handle major parts of semiconductor design if human engineers still controlled final verification and signoff?