CXMT Targets 4F² DDR5 RDIMM by Year End as China Accelerates DRAM Expansion
China's ChangXin Memory Technologies is preparing another major step in its DRAM roadmap, with company President Dr. Cao Kanyu announcing plans to introduce a new generation of DDR5 RDIMM products incorporating 4F² memory cell architecture and other advanced technologies before the end of 2026.
Cao presented the roadmap during the 4th Integrated Chip and Chiplet Conference in Shanghai on October 10. According to IT Home, CXMT has recently achieved key development progress with its 4F² DRAM architecture and expects its first product incorporating the technology to target DDR5 RDIMM, placing the new architecture directly into the demanding server memory segment. Specific capacity, data rate, voltage, process node, qualification status, and exact availability were not disclosed.
Current mainstream DRAM typically uses a 6F² cell layout, where each memory cell occupies an area equivalent to 6 times the square of the minimum feature size. Moving to 4F² reduces that theoretical footprint to 4F², allowing manufacturers to place more memory cells within the same silicon area. Industry estimates suggest the architecture could improve density by roughly 30% to 50%, although the actual advantage depends heavily on the transistor design, process technology, yield, and implementation.
| DRAM Development | Current or Reported Direction |
|---|---|
| Mainstream Architecture | 6F² |
| CXMT Next Generation Architecture | 4F² |
| CXMT First Planned Application | DDR5 RDIMM |
| CXMT Product Target | Before the end of 2026 |
| Samsung 4F² Status | Working 10a engineering die reported |
| Samsung Reported Mass Production Target | 2028 |
Moving from 6F² to 4F² is considerably more complicated than simply shrinking the existing cell. CXMT has investigated vertical transistor structures, word line metallization, bit line formation, junction activation, and hybrid bonding as part of the new architecture. Cao said CXMT began researching and filing patents around 4F² shortly after the company's foundation and now has more than 300 published patent families associated with the technology. CXMT also published research related to 4F² in 2021, followed by additional development disclosures in 2023 and 2025.
The server focus makes the announcement particularly ambitious. DDR5 RDIMMs need to meet much stricter requirements around continuous operation, signal integrity, error handling, platform validation, and long term reliability than typical consumer memory. Introducing a new DRAM cell architecture through server memory therefore creates significant engineering and qualification challenges beyond simply demonstrating a functioning die.
Very interesting Samsung plans to introduce 4F² in 2028
— Zephyr (@zephyr_z9) October 10, 2026
The announcement has generated comparisons with Samsung because the South Korean manufacturer is reportedly targeting 2028 for mass production of its own 4F² DRAM. However, describing CXMT as being 2 years ahead requires important context. Samsung reportedly produced a functioning 10a DRAM engineering die using 4F² cells and Vertical Channel Transistors earlier in 2026, with development expected to continue through 2026, qualification during 2027, and mass production in 2028. CXMT, meanwhile, has announced a product target for the end of 2026 without disclosing whether that milestone represents samples, limited production, customer qualification, or mature high volume manufacturing.
The 2 timelines therefore are not directly equivalent. If CXMT delivers working 4F² DDR5 RDIMMs before the end of 2026, it would represent a major product milestone, but stable mass production, competitive yields, server qualification, and meaningful shipment volume will ultimately determine whether the company has achieved a manufacturing advantage.
CXMT started mass production of G5, a noteworthy milestone indicating the move to SAQP as a key part of the manufacturing process. A subsequent node transition to G6 can be predicted as a natural followup to G5 before going to monolithic 3D DRAM. https://t.co/G6jiAguvZB https://t.co/FYwFSXsKBC
— Fred Chen (@DrFrederickChen) October 10, 2026
SK hynix is developing a similar direction. The company publicly outlined its future 4F² Vertical Gate DRAM roadmap in 2025 as conventional DRAM scaling approaches its physical limitations, positioning 4F² and eventually 3D DRAM as technologies required for future density improvements. Tokyo Electron's broader industry roadmap similarly places 4F² Vertical Channel Transistor structures among the technologies expected to succeed today's 6F² designs.
CXMT also has significantly more manufacturing scale behind its technology roadmap than it did only a few years ago. The company currently operates 3 major 300 mm DRAM fabs, 2 in Hefei and 1 in Beijing, with combined production capacity reported at approximately 300,000 wafers per month. Additional projects could eventually push that figure beyond 600,000 wafers per month if planned expansion is completed. Reuters has separately reported that CXMT's current monthly output is around 300,000 wafers and could double as new capacity comes online.
That manufacturing expansion accompanies rapid improvements elsewhere in CXMT's business. The company has already become the world's 4th largest DRAM supplier, while its DDR5 manufacturing yields have reportedly moved above 90% and its products are increasingly entering server and international consumer memory markets. CXMT's rising scale means a successful 4F² architecture could become commercially significant rather than remaining a laboratory demonstration.
Export restrictions remain an important limitation. CXMT does not have the same access to advanced EUV lithography as Samsung, SK hynix, and Micron, forcing the company to extract more capability from DUV based manufacturing while developing alternative transistor structures, bonding technologies, and increasingly domestic semiconductor equipment. This makes 4F² strategically important because density improvements can potentially come from structural changes rather than relying entirely on conventional lithographic scaling.
CXMT's announcement is significant, but the real benchmark is not whether it can put a 4F² DDR5 RDIMM on stage before Samsung reaches mass production.
Samsung already has working 4F² silicon, SK hynix has publicly outlined its own Vertical Gate strategy, and the entire DRAM industry is moving toward new cell architectures as conventional 6F² scaling becomes increasingly difficult.
What changes the equation for CXMT is scale. A company operating around 300,000 wafer starts per month, with expanding DDR5 production and increasingly competitive yields, has the manufacturing base to turn an architectural breakthrough into meaningful market supply if the technology works reliably.
The critical numbers CXMT has not disclosed are therefore the ones to watch next: die density, yield, power efficiency, frequency, module capacity, customer qualification, and production volume. If those metrics become competitive, CXMT's 4F² program could represent a much more consequential challenge to Samsung, SK hynix, and Micron than simply arriving first on a roadmap.
Could CXMT's aggressive 4F² roadmap turn China into a genuine technology competitor in server DRAM, or will manufacturing yield and qualification remain the biggest barriers?
