TSMC Reportedly Develops EMIB Like Packaging as CoWoS Capacity Tightens
TSMC is reportedly developing a new advanced packaging technology designed to compete more directly with Intel’s EMIB architecture as demand continues to overwhelm its existing CoWoS production capacity. A report from The Information, claims the project is internally described as quasi EMIB and is being developed alongside Taiwanese substrate manufacturer Kinsus Interconnect Technology. TSMC has not officially announced the project or disclosed its technical configuration.
The reported initiative arrives as Intel’s Embedded Multi die Interconnect Bridge gains attention as an alternative for large AI and high performance computing packages. Traditional TSMC CoWoS S places processors and High Bandwidth Memory on a large silicon interposer, providing extensive high density routing across the package. CoWoS L reduces dependence on a full silicon interposer by using a redistribution layer interposer combined with localized silicon interconnect bridges where dense communication is required.
Intel EMIB follows a different structure by embedding small silicon bridges directly inside the organic package substrate. Dense connections are placed only where neighboring chiplets need to communicate, avoiding a package wide interposer. EMIB T expands the design with through silicon vias for vertical power delivery, HBM connectivity, and larger multidie systems. Intel says its 2026 roadmap supports packages exceeding 8 times reticle size, approximately 120 by 120 mm, with 12 HBM stacks and more than 20 EMIB bridges.
| Technology | Packaging Structure | Primary Advantage | Current Position |
|---|---|---|---|
| TSMC CoWoS S | Large silicon interposer beneath logic and HBM | Uniform high density routing across the package | Established volume production |
| TSMC CoWoS L | Redistribution layer interposer with localized silicon interconnect bridges | Supports larger packages while reducing reliance on a full silicon interposer | Volume production since 2024 |
| Intel EMIB T | Silicon bridges embedded directly inside the package substrate with through silicon vias | Localized dense connections, vertical power delivery, and greater package scalability | Expanding toward large AI and HPC designs |
| Reported TSMC Quasi EMIB | Undisclosed EMIB like architecture reportedly developed with Kinsus | Could simplify bridge based integration and increase packaging flexibility | Unconfirmed development project |
The competitive pressure is not limited to architecture. TSMC Chairman and CEO C.C. Wei recently acknowledged that advanced packaging demand is restricting customer growth. He also welcomed additional industry capacity, noting that alternative packaging providers could absorb some workloads while TSMC continues manufacturing the leading process wafers used inside those packages.
"Our packaging capacity is so tight that now it limits my customers’ growth."
— Quote by: C.C. Wei.
Intel has meanwhile been expanding EMIB capacity through major equipment orders across multiple production locations. MediaTek has also confirmed support for both TSMC CoWoS and Intel EMIB, allowing custom silicon customers to choose between the competing platforms. These developments indicate that advanced packaging is becoming an independent competitive market rather than simply an extension of wafer manufacturing.
The reported quasi EMIB project should still be treated cautiously. Wccftech suggests TSMC could remove the separate redistribution layer and adopt bridges embedded directly inside the substrate, but this remains an interpretation rather than a confirmed technical specification. Until TSMC or Kinsus publishes additional details, the project is best understood as evidence that bridge based packaging is gaining strategic relevance across the AI supply chain.
TSMC does not need to abandon CoWoS to respond to Intel. Its immediate priority is increasing capacity while giving customers more architectural options for packages that do not require a large continuous interconnect plane. A simpler bridge based solution could complement CoWoS S and CoWoS L rather than replace them.
For Intel, the reported project is meaningful validation. EMIB is no longer being discussed only as an internal packaging technology. It is becoming influential enough for competitors, custom silicon developers, and memory suppliers to evaluate similar approaches. However, architecture alone will not decide the market. Yield, production scale, substrate availability, design tools, pricing, and delivery reliability will determine whether Intel can convert technical momentum into sustained external business.
Could advanced packaging become Intel’s strongest opportunity to challenge TSMC, or will CoWoS capacity expansion protect TSMC’s market leadership?
