Samsung Breaks the 10nm DRAM Barrier With New 4F Cell Structure That Could Boost Density by Up to 50%

Samsung Electronics has reportedly produced the world’s first working DRAM die using a process technology below 10nm, marking a major technical milestone for the memory industry as demand for AI, servers, and high density DRAM continues to accelerate. According to The ELEC, Samsung confirmed a working die after producing wafers with its next generation 10a DRAM process, which is believed to scale down to around 9.5nm to 9.7nm.

For years, the DRAM industry has operated within the 10nm class generation, using naming such as 1x, 1y, 1z, 1a, 1b, 1c, and 1d. Samsung’s 10a node represents the next step beyond 1d and is being described as the first true single digit nanometer DRAM process. The company reportedly plans to use the working die to adjust process conditions, improve yields, and accelerate development toward production readiness.

The breakthrough comes from Samsung’s first application of a 4F square cell structure and a Vertical Channel Transistor process, also known as VCT. These 2 changes are critical because conventional DRAM scaling has become increasingly difficult as cells shrink. Traditional DRAM products commonly use a 6F structure, where each cell has a rectangular 3F by 2F layout. Samsung’s new 4F square structure changes that to a 2F by 2F layout, allowing significantly more cells to fit within the same die area.

The theoretical benefit is substantial. By moving from 6F to 4F, DRAM makers can increase cell density by roughly 30% to 50%. Higher density means more memory capacity per chip, better scaling potential, and possible power efficiency gains. For AI servers, HPC systems, consumer PCs, and next generation mobile devices, this kind of density improvement is becoming increasingly important as workloads continue demanding more memory.

The VCT process is another major part of Samsung’s strategy. In conventional DRAM, the transistor and capacitor occupy space across the cell structure. With VCT, Samsung places the capacitor above the transistor, helping solve the layout challenge created by the smaller 4F square cell. The company is also reportedly using a Periphery Under Cell approach, where peripheral circuits such as sense amplifiers, test circuits, timing controllers, and voltage circuits are processed on a separate wafer and attached underneath using wafer to wafer hybrid bonding.

This is a major architectural shift for DRAM. It shows that Samsung is not only shrinking the process node, but also changing how the DRAM cell and surrounding circuitry are organized. As traditional 2D scaling becomes harder, structural innovation becomes just as important as lithography.

Samsung is also reportedly changing key materials. The new DRAM process uses Indium Gallium Zinc Oxide, or IGZO, as the channel material instead of conventional silicon. IGZO is used to reduce leakage current in the narrower cells and help improve data retention. This is especially important as DRAM cells shrink because smaller cells are more vulnerable to leakage, retention loss, and reliability challenges.

Samsung may also change the wordline material. The company reportedly considered replacing titanium nitride with molybdenum because molybdenum offers lower resistance and can provide a wider current path at the same line width. However, molybdenum is more difficult to process due to its corrosive characteristics and production equipment requirements, so Samsung may continue using titanium nitride depending on final process decisions.

The roadmap is also significant. Samsung reportedly plans to complete development of 10a DRAM this year, conduct quality testing next year, and transfer the technology to mass production lines in 2028. The 4F square and VCT structure is expected to be used across the 10a, 10b, and 10c generations, while 10d is expected to move toward 3D DRAM around the 2029 to 2030 timeframe.

That makes 10a more than just another DRAM shrink. It is a bridge between today’s planar DRAM and the future transition to true 3D DRAM. According to industry discussion cited by The ELEC, VCT can be seen as a key stepping stone toward 3D DRAM, because rotating and stacking this structure horizontally could form the basis of future 3D memory designs.

The competitive landscape is also changing. Micron is reportedly holding off on 4F square and VCT adoption, choosing instead to extend existing DRAM designs until it moves more directly toward 3D DRAM. SK hynix is reportedly planning to apply 4F square and VCT technology at the 10b generation rather than 10a. This means Samsung may gain an early technical advantage if it can stabilize yield and reliability ahead of competitors.

Chinese DRAM manufacturers face a different challenge. Without access to the most advanced EUV lithography equipment, shrinking DRAM through traditional methods becomes increasingly difficult. However, if 3D DRAM eventually follows a structure similar to 3D NAND, where vertical scaling can reduce dependence on the most advanced lithography steps, Chinese memory makers may see 3D DRAM as a possible path forward. That is one reason multiple companies are accelerating 3D DRAM research.

For the broader industry, Samsung’s reported working die comes at a critical moment. AI demand is reshaping the entire memory market. HBM receives most of the attention because of AI accelerators, but conventional DRAM scaling still matters across servers, PCs, mobile devices, edge systems, and future AI platforms. Higher density DRAM can help improve capacity, reduce power consumption, and support more memory hungry workloads.

If Samsung successfully commercializes 10a DRAM, it could strengthen the company’s position in a memory market currently driven by AI demand, HBM competition, and server capacity expansion. However, reaching a working die is only the beginning. The real challenge will be securing production yield, reliability, retention stability, process repeatability, and cost efficiency at scale.

The significance of the working die is that it shows the design and process direction are viable. Now Samsung must turn that technical proof into a manufacturable product. If the company reaches mass production in 2028 as planned, 10a DRAM could become one of the most important memory milestones of the decade.

Samsung’s sub 10nm DRAM achievement shows that the DRAM industry still has room to push density forward before fully transitioning to 3D DRAM. With 4F square cells, VCT, IGZO materials, and hybrid bonding strategies, the company is preparing a new generation of memory technology designed for the AI era.

Will Samsung’s 4F and VCT DRAM strategy give it a major advantage before the industry shifts to 3D DRAM?