JEDEC Approves SPHBM4 to Bring HBM4 Class Bandwidth to More Affordable Packages
JEDEC has approved SPHBM4, a new Standard Package High Bandwidth Memory specification designed to preserve the massive data throughput associated with HBM4 while reducing dependence on the expensive silicon interposers and advanced packaging processes currently limiting AI accelerator production.
The new standard arrives as demand for HBM continues to surge across artificial intelligence and high performance computing. NVIDIA, AMD, custom accelerator developers, and cloud providers are consuming increasingly large volumes of advanced memory, but producing more HBM stacks is only one part of the challenge. Those stacks must also be integrated beside large compute dies through extremely dense package connections, making packaging capacity, manufacturing yield, and interposer cost critical parts of the supply chain.
According to ETNews, SPHBM4 received final approval from the JEDEC Board of Directors following development through the JC 42.2 DRAM memory subcommittee. The standard is intended to offer HBM4 class aggregate bandwidth through a much narrower connection that can be routed across more conventional package substrates.
HBM achieves its performance through an extremely wide interface. Standard HBM4 uses 2,048 data signals between each memory stack and the host processor. That approach delivers enormous bandwidth, but it also requires thousands of tightly packed connections and a highly advanced silicon interposer or comparable integration technology.
SPHBM4 changes that equation by using 512 data signals with 4:1 serialization. The interface therefore carries more information through each connection instead of relying on the full 2,048 signal width of conventional HBM4.
The approved architecture reportedly increases signal speed to as much as 32 Gbps per pin, approximately 4 times the standard JEDEC HBM4 data rate. By moving more data through every signal, SPHBM4 can target similar aggregate throughput while using one quarter of the data connections. ETNews describes the broader reduction across required signal pins as approximately one fifth, depending on which control and supporting connections are included.
This does not mean SPHBM4 will behave identically to HBM4 in every measurement. Aggregate bandwidth may remain comparable, but latency, power consumption, signal integrity, controller complexity, and real workload performance will depend on the final memory stacks, base dies, package designs, and host processors.
The narrower interface offers a major packaging advantage. Reducing the number of required connections allows manufacturers to use a wider connection pitch, making it possible to place SPHBM4 on standard organic substrates instead of depending entirely on dense silicon interposers.
That could reduce one of the largest expenses surrounding HBM integration. Conventional HBM is not costly only because of its vertically stacked DRAM dies and through silicon vias. The complete accelerator package also requires advanced interposers, precise assembly, dense routing, complex power delivery, and extensive testing.
“SPHBM4 targets a fourfold increase in signal speed versus HBM4, thereby cutting the required signal pin count to roughly one fifth. Its defining feature is the ability to deliver HBM class bandwidth while using standard substrates.”
— Vikram Sekar (@vikramskr) June 21, 2026
HBM4 has ~2K pins and each pin runs at 11Gbps… https://t.co/6GEVuIO4md
SPHBM4 will still require sophisticated manufacturing. The memory continues using stacked DRAM dies, through silicon vias, and a dedicated interface base die. However, removing or reducing the need for a full silicon interposer could make HBM class memory available to a wider range of accelerator companies that cannot secure the same packaging capacity as NVIDIA, AMD, and the largest hyperscalers.
The longer supported connection distance could provide another advantage. ETNews reports that SPHBM4 defines a connection between the compute die and memory reaching up to 20 mm. Traditional HBM stacks must remain extremely close to the processor because of the wide parallel interface and strict signal requirements.
A longer channel gives package designers more freedom when positioning memory around large processors, chiplets, networking dies, and power delivery systems. It could also improve thermal management by allowing memory stacks to sit farther away from the hottest parts of an AI accelerator.
This increased flexibility may become especially valuable as AI packages continue growing. Future accelerators will combine more compute chiplets, larger networking systems, more memory stacks, and increasingly complicated power delivery inside one package. A memory interface that can travel farther across the substrate could help designers avoid severe thermal concentration around the main compute dies.
The change may also allow systems to use more SPHBM4 stacks. JEDEC’s earlier explanation indicated that SPHBM4 would use the same DRAM core layers as HBM4, meaning the capacity available from each stack could remain comparable. Longer routing distances and less restrictive placement could allow designers to install additional stacks and increase the total memory capacity available to an accelerator.
That could make SPHBM4 particularly valuable for inference, where large language models and extensive context data must remain close to compute. Training systems need extreme bandwidth, but modern agentic AI also requires enough capacity to hold model weights, retrieval data, memory states, and multiple active workloads. Other technologies such as ZAM, CXL attached memory, 3D stacked flash, and expanded memory hierarchies are also being developed. SPHBM4 is different because it does not attempt to replace HBM with another memory medium. It keeps the HBM4 DRAM foundation while changing how that memory connects to the processor.
This could give SPHBM4 a more direct route into future AI accelerators. Memory manufacturers can reuse HBM4 class core dies while developing a new interface base die, and accelerator companies can design controllers around a JEDEC standard instead of adopting one proprietary memory architecture.
However, faster signal rates bring their own engineering problems. A 32 Gbps connection needs stronger equalization, clocking, error control, signal integrity, and power management than the slower parallel interface used by HBM4. Some of the complexity removed from the substrate therefore moves into the memory base die, host controller, and physical interface.
The industry will need to prove that this trade is economically worthwhile. Lower package cost could be offset if the faster interface consumes significantly more power, requires expensive controller silicon, or creates difficult validation requirements. The technology must also maintain reliability across longer package connections and the extreme temperatures found inside dense AI systems.
SPHBM4 should not be viewed as a replacement for GDDR memory in consumer graphics cards. GDDR remains much easier and cheaper to deploy across gaming products, with memory chips positioned around the GPU on a conventional board. SPHBM4 remains a stacked memory technology aimed primarily at AI accelerators, high performance computing systems, and other products requiring enormous bandwidth and capacity.
Glass substrates could eventually strengthen the design further. Industry analysts believe SPHBM4 may fit naturally into the extremely large packages expected to use glass core substrates because glass offers better flatness, dimensional stability, thermal behavior, and fine wiring than conventional organic materials.
An industry source speaking with ETNews described SPHBM4 as a standard that could enable more economical placement of HBM class memory across large packages built on glass.
"SPHBM4 is a standard that enables the more economical placement of HBM class memory within them." Quote by: Industry source speaking with ETNews.
Glass is not required for SPHBM4, and it remains several years away from widespread commercial production. We covered how Intel backed glass substrate packaging could reach commercialization within approximately 3 years, but manufacturers must still solve issues involving drilling, metallization, handling, breakage, yield, and mass production cost.
If both technologies mature, glass substrates could provide the stable foundation needed for enormous AI packages, while SPHBM4 supplies HBM class bandwidth without forcing every connection through an expensive silicon interposer.
The approval also arrives as memory suppliers deepen their partnerships with AI chipmakers. NVIDIA and SK hynix formed a multiyear agreement to develop memory for future AI factories. Samsung, Micron, and SK hynix are already increasing HBM4 production and sampling HBM4E, but demand continues expanding faster than capacity can be added. SPHBM4 will not immediately solve the shortage. JEDEC approval provides the common specification, but memory manufacturers must still design products, accelerator companies must create compatible controllers, and packaging partners must qualify the complete systems. No commercial launch date has been announced.
The standard could nevertheless change the economics of future AI hardware. Conventional HBM concentrates production among companies with access to the most advanced packaging capacity. A standard that supports organic substrates could open the market to additional foundries, packaging providers, accelerator developers, and system manufacturers.
SPHBM4 represents an important change in how the industry is approaching the memory wall. The answer is no longer only to make HBM faster, stack more DRAM, or build larger silicon interposers. JEDEC is redesigning the connection itself so HBM class performance can reach packages that are easier to manufacture and potentially more affordable.
The most important test will come when the first products arrive. SPHBM4 must prove that its faster serial interface can preserve bandwidth without creating unacceptable power, latency, or signal integrity penalties. It must also deliver meaningful package savings after the cost of new base dies, controllers, and validation is included.
If those conditions are met, SPHBM4 could become one of the most important memory standards of the AI era. It would not replace premium HBM4 or HBM4E in every accelerator, but it could provide a second path for companies that need enormous bandwidth without accepting the full cost and packaging complexity of conventional HBM.
Question for readers
Could SPHBM4 make HBM class memory accessible to more AI chipmakers, or will its 32 Gbps interface introduce new power and signal challenges that offset the packaging savings?
