Former Intel CEO Pat Gelsinger is backing a new memory technology that could address one of the biggest limitations facing modern AI accelerators. Developed by Nagare Labs, Z2RAM aims to combine the speed of SRAM, the density of DRAM, and the vertical scalability of NAND flash memory within a single architecture. The company emerged from stealth on October 26, 2026, announcing $5 million in funding from Playground Global, where Gelsinger serves as a general partner. He has also joined Nagare Labs as a board director, supporting its efforts to bring the technology into commercial semiconductor manufacturing.
Founded by Georgia Tech researchers Suman Datta and Shimeng Yu, Nagare Labs is developing Z2RAM around a capacitorless memory cell containing 2 transistors instead of the conventional 1 transistor and 1 capacitor design used by DRAM. The architecture uses oxide semiconductor materials and stores electrical charge through the gate capacitance of a transistor, enabling nondestructive reads and potentially reducing access latency. Unlike conventional SRAM, which typically requires 6 transistors per bit, Z2RAM is designed to achieve greater density through vertically stacked memory layers.
The technology could be particularly valuable for AI accelerators, where High Bandwidth Memory (HBM) is typically positioned beside the processing die and connected through an interposer. Moving data between memory and computing hardware consumes significant energy and introduces latency, even with the substantial bandwidth provided by HBM. Z2RAM proposes depositing multiple memory layers on a single die integrated directly above the accelerator, shortening data paths and enabling more vertical connections across the chip.
Speaking in an October 26 interview, Gelsinger described the technology as combining the strongest characteristics of existing memory architectures.
"Dense like DRAM, fast like SRAM, and scalable like flash."
— Quote by: Pat Gelsinger, Former Intel CEO
Z2RAM Projected Performance Improvements
| Metric | Z2RAM Generation 1 Target |
|---|---|
| Memory Architecture | 2 transistors, no capacitor |
| Access Speed | Up to 14x faster than DRAM |
| Bit Density | Up to 5x greater than SRAM |
| Read Energy | Up to 3x lower than SRAM |
| Initial Memory Layers | 6 vertically stacked layers |
| Manufacturing | Standard 300 mm wafer processes |
| Integration | Memory stacked directly above compute |
All performance figures are company projections for Generation 1, not independently validated commercial product benchmarks.
According to the official technology announcement, Z2RAM is designed around manufacturing materials and processes already familiar to semiconductor foundries, potentially reducing the cost and complexity of scaling production. However, the technology remains at the laboratory prototype stage. Nagare Labs is seeking manufacturing partners, with initial memory samples targeted within approximately 4 years and commercial shipments potentially arriving within the next decade. Reliability, production yields, and industry standard integration interfaces remain significant challenges.
The development comes as the global memory industry faces potential shortages through 2030, driven by growing demand for HBM and server DRAM. While Z2RAM could eventually introduce another memory option for AI accelerators, it is not an immediate replacement for HBM or conventional DDR5. Its primary opportunity lies in reducing data movement and improving memory efficiency within increasingly complex computing systems.
Z2RAM represents an interesting potential shift in semiconductor architecture, particularly because it targets memory efficiency rather than relying exclusively on greater bandwidth or more advanced manufacturing nodes. Integrating dense memory directly above processing logic could benefit future AI accelerators and potentially influence CPU and GPU cache designs. However, laboratory demonstrations are only the first step. Manufacturing scalability, thermal reliability, and integration costs will determine whether the technology can compete with established DRAM and SRAM solutions. With memory supply constraints expected to continue for several years, alternative architectures like Z2RAM could become increasingly important to the long term development of high performance computing.
Could Z2RAM become a serious alternative to HBM and traditional SRAM, or will established memory technologies continue dominating AI accelerators and gaming hardware?
