TSMC Races to Expand Advanced Packaging Capacity as AI Demand Risks Outrunning Supply
TSMC is moving more aggressively to relieve one of the most important bottlenecks in the AI hardware chain: advanced packaging. A new report from CNA says the company is preparing a much broader packaging buildout across Taiwan, with plans that extend from CoWoS and SoIC to WMCM and CoPoS. The reported strategy reflects a simple reality now shaping the semiconductor market: leading edge wafers alone are no longer enough. If advanced packaging capacity does not keep rising quickly, even the best chip roadmaps can get stuck before they ever reach customers.
According to CNA, TSMC is expected to equip 7 facilities with advanced packaging related capabilities in Taiwan, while also gradually converting older 8 inch fabs into packaging oriented sites to support the next wave of AI and high performance computing demand. The report says TSMC already has 5 advanced packaging and testing facilities in Hsinchu, Tainan, Longtan, Taichung, and Zhunan, with Chiayi’s advanced packaging site becoming the company’s largest such base in Taiwan. It also points to a possible eighth advanced packaging site in Tainan, reinforcing how central packaging has become to TSMC’s expansion plans.
The scale of the expected ramp is significant. CNA says industry estimates now point to TSMC’s CoWoS led advanced packaging capacity rising from about 1.3 million wafers in 2026 to roughly 2 million wafers by 2027. Earlier CNA reporting also cited estimates that monthly CoWoS capacity could rise from around 70000 wafers at the end of 2025 to 100000 to 115000 wafers by the end of 2026, before climbing further in 2027. That kind of expansion is not incremental. It signals a company trying to prevent packaging from becoming the hard ceiling on AI accelerator shipments.
This matters because advanced packaging has become one of the most valuable links in the AI supply chain. CoWoS is critical for large AI processors that need to pair leading logic dies with stacks of HBM, while SoIC and WMCM support other high density integration paths for premium compute and mobile designs. TSMC itself has previously said it will bring larger 9.5 reticle CoWoS into volume production in 2027 to support packages with 12 HBM stacks or more, underlining just how fast package complexity is growing in the AI era.
The pressure is not limited to Taiwan. TSMC’s Arizona buildout is increasingly part of the same conversation. The company officially announced in 2025 that it plans to expand its total United States investment to 165 billion dollars, including 2 advanced packaging facilities and an R&D center in Arizona. CNA now reports that the first Arizona advanced packaging plant is expected to enter mass production in 2028, with the second following around 2029 to 2030, focusing mainly on SoIC and CoPoS. That is strategically important because TSMC’s U.S. wafer output is growing, but without more local packaging capacity, the full AI manufacturing chain in Arizona remains incomplete.
There is also a more immediate risk behind all of this. If TSMC cannot add packaging capacity fast enough, customers do have alternatives to explore. Intel continues to position EMIB and related advanced packaging technologies as viable options, and OSAT players such as Amkor are expanding in Arizona as well. Amkor’s Arizona packaging campus is expected to begin production in early 2028 and already has Apple and Nvidia lined up as lead customers, showing that the ecosystem is preparing for a world where packaging is no longer a back end afterthought but a primary competitive lever.
At the same time, TSMC still appears to be in a strong position. Reuters reported this week that demand for advanced packaging tied to AI remains above TSMC’s current production capacity, helping drive expectations for another record quarter. The company also previously said that advanced packaging contributed close to 10% of revenue in 2025 and is expected to exceed 10% in 2026, which shows this is not just a support business anymore. It is becoming a larger and more strategic revenue engine in its own right.
The broader takeaway is clear. The AI race is no longer decided only by who has the best process node or the biggest GPU. It is increasingly being decided by who can package the most advanced chips at scale, on time, and close enough to key customers to keep delivery schedules intact. TSMC seems to understand that, and its latest moves suggest the company is now treating advanced packaging as a front line growth priority rather than a secondary support function. That is likely the correct call, because in the current market, every unbuilt packaging line is a future shipment that risks going elsewhere.
Do you think advanced packaging has now become the most important bottleneck in the AI chip race, or will wafer capacity retake center stage once the current CoWoS crunch eases?
