TSMC and Intel Accelerate Glass Packaging Race as Market Targets $8.1 Billion

TSMC, Intel, and several major semiconductor packaging companies are accelerating investments in Fan Out Panel Level Packaging and glass substrates as artificial intelligence and high performance computing processors push conventional organic substrates and wafer based packaging closer to their practical limits. According to the latest Counterpoint Research FOPLP and Glass Substrate Packaging Report, the combined market is forecast to grow from approximately $650 million in 2024 to more than $8.1 billion by 2030. AI and HPC applications are expected to become the largest growth drivers, representing 45.6% of total FOPLP revenue by the end of the decade.

The transition is being driven by increasingly large AI accelerators that combine multiple compute chiplets, high bandwidth memory stacks, networking dies, and power delivery components inside a single package. Traditional circular wafer formats create unused space around the edges, while larger rectangular panels can process more packages simultaneously and support designs that extend beyond conventional reticle and package size limits.

Glass substrates are also attracting attention because they provide stronger dimensional stability, improved flatness, better warpage control, and the potential for significantly denser electrical connections compared with organic materials. These characteristics are becoming increasingly important as AI processors grow physically larger and require more complex signal routing between compute dies and memory.

"As package complexity continues to increase, glass substrates are gaining industry attention as a potential alternative to traditional organic substrates. Compared with organic materials, glass substrates offer advantages in interconnect density, dimensional stability and warpage control, supporting the development of next generation chiplet based architectures and large AI processors."
— Yoshio Tamura, Vice President of Research at Counterpoint Research

TSMC is developing its CoPoS platform, meaning Chip on Panel on Substrate, as a panel based successor and complement to its established CoWoS packaging ecosystem. According to TrendForce, TSMC has standardized its current CoPoS development around a 310 × 310 mm panel format, with supplier validation taking place during 2026, pilot production targeted for 2027, and mass production planned for the second half of 2028.

The first CoPoS generations are expected to continue using organic substrates before TSMC transitions toward glass core materials in later versions. TrendForce currently expects commercial scale glass core substrate production connected to TSMC to become more realistic after 2030, reflecting the considerable manufacturing challenges that remain.

WCCFTCH estimates suggest that rectangular panel processing could improve material utilization from below 70% to more than 90% while reducing packaging costs by around 30%. However, these figures remain projections and will depend heavily on production yield, panel size, process maturity, and the complexity of the packaged processor.

Intel has been publicly developing glass substrates for more than a decade and officially presented the technology in 2023. The company said its glass platform could deliver up to 10 times greater interconnect density, 50% lower pattern distortion, stronger thermal stability, and support for substantially larger multi chip packages.

Intel expects its first complete glass substrate packaging solutions to reach customers during the second half of this decade, initially targeting data center, AI, and graphics workloads. Its Arizona facilities have supported glass substrate research and testing, while its Rio Rancho operations in New Mexico are becoming an important United States manufacturing base for advanced packaging technologies. Intel backed glass substrate packaging could enter commercialization within 3 years, following comments from Amkor that technical stability and packaging stress concerns were beginning to improve.

Other companies including Samsung Electro Mechanics, ASE, PTI, Amkor, SKC subsidiary Absolics, and multiple Japanese material suppliers are also expanding their glass and panel packaging development. This growing supply chain will be essential because advanced packaging is no longer a secondary manufacturing step. It is becoming one of the most important performance, cost, and capacity factors for future AI processors.

Counterpoint expects Taiwan, Japan, and Mainland China to represent 84.8% of global panel level packaging capacity by 2030. Taiwan already holds a strategic advantage through its foundry, packaging, equipment, and display manufacturing ecosystem, while Japan is expected to record particularly strong growth through investment in glass materials and substrate production.

Despite the growing investment, several major obstacles still need to be resolved. The industry has not established a universal panel size standard, while Through Glass Via production must deliver consistent hole dimensions, reliable metallization, and low defect rates across very large panels. Manufacturers must also control microscopic cracking, thermal expansion differences, alignment accuracy, and warpage during high volume production.

Maintaining nanometer level flatness becomes increasingly difficult as panel dimensions exceed 500 × 500 mm. These challenges mean that glass substrates and FOPLP are unlikely to replace organic substrates or wafer based packaging immediately. Instead, they are expected to enter the market gradually through the largest and most expensive AI and HPC processors, where their performance and package size advantages can justify the additional manufacturing complexity.

The move toward panels and glass is not simply another material transition. It represents a fundamental redesign of how the semiconductor industry intends to assemble the largest processors of the next decade. AI accelerators are becoming systems rather than individual chips, combining CPUs, GPUs, networking, HBM, optical connections, and power delivery into increasingly complex packages. At that scale, packaging technology directly determines how much compute, memory bandwidth, and connectivity can be placed inside a deployable product.

TSMC currently holds the strongest commercial position because of its CoWoS ecosystem, customer relationships, and advanced packaging scale. However, Intel could build a meaningful competitive advantage if it commercializes glass substrates before its rivals and combines them with EMIB, Foveros, and its broader foundry services.

The market forecast of more than $8.1 billion by 2030 shows that advanced packaging is rapidly becoming a strategic semiconductor sector of its own. The companies that solve panel yield, glass reliability, and Through Glass Via consistency will influence not only manufacturing cost, but also the physical design of future AI systems.

Do you think glass substrates and panel level packaging will become the next major semiconductor manufacturing standard, or will production complexity keep organic substrates dominant beyond 2030?