Google Reportedly Taps MediaTek for TPUv9 Triggerfish With HBM4E and Expanded SRAM

Google is reportedly deepening its custom AI silicon partnership with MediaTek through an upgraded TPUv9 accelerator internally known as Triggerfish. The design is expected to combine substantially larger SRAM, HBM4E memory, and a new companion die intended to reduce coordination overhead across inference, training, reinforcement learning, and agentic AI workloads.

The roadmap has not been officially announced by Google, MediaTek, Intel, or TSMC. The information currently comes from supply chain reporting, including a Wccftech report based partly on information from FundaAI, details shared by Jukan, and a separate industry assessment from analyst Ming Chi Kuo. Until the companies involved publish technical documentation, the specifications, production dates, and supplier responsibilities should be treated as credible but unconfirmed reporting.

Update: pic.twitter.com/xnr0dKYZvg

— Jukan (@jukan05) June 23, 2026

The reported TPUv9 direction follows Google’s official introduction of its 8th generation TPU family. In its official TPU 8 announcement, Google divided the generation into TPU 8t for large scale training and TPU 8i for latency sensitive inference. The company explained that both processors can support different parts of the AI lifecycle, but their specialized architectures allow each design to target a specific performance and efficiency profile.

Google and MediaTek Deepen TPU v9 Collaboration with Upgraded Triggerfish, Targeting AI Agents, Reinforcement Learning, and Effective Compute Maximization

1. My latest industry checks indicate that Google is developing an upgraded v9 chip, likely codenamed Triggerfish, based on…

— 郭明錤｜Ming-Chi Kuo (@mingchikuo) June 22, 2026

Google’s technical overview of TPU 8t and TPU 8i also describes how the systems use Axion CPU hosts to manage preprocessing and orchestration, reducing the risk of accelerators being left waiting for data. Separate supply chain reports associate the TPU 8i design, commonly identified as Zebrafish, with MediaTek, while TPU 8t, commonly identified as Sunfish, has been associated with Broadcom. Google did not identify those external design partners in its official announcement.

Triggerfish is reportedly being developed as an upgraded extension of another TPUv9 design called Humufish. According to Kuo, the main architectural changes include SRAM capacity increasing to approximately 2 to 3 times that of Humufish, a transition from HBM4 to HBM4E, and the addition of a simulation die intended to support local TPU management, workload switching, reinforcement learning, and coordination between AI agents.

One technical detail varies between reports. Information attributed to FundaAI describes the added component as a CPU tile placed in the same package as the main compute die. Kuo instead refers to it as a simulation die. Both descriptions assign the component a similar operational role, including local management and switching between training and inference modes, but its exact architecture has not been confirmed.

The larger SRAM allocation could be one of Triggerfish’s most important upgrades. SRAM positioned close to the compute engines can retain more active model data, agent state, and reinforcement learning workloads inside the accelerator package. This reduces the need to repeatedly transfer data between the TPU, host CPU, and external memory.

That approach is designed to address both the memory wall and the CPU wall. Modern AI accelerators often have enormous theoretical compute capability, but performance can fall below that potential when data movement, host coordination, or memory latency prevents the compute engines from remaining fully utilized. Agentic AI increases this pressure because agents must evaluate multiple steps, exchange information, call tools, update state, and react with minimal delay.

Production forecasts also vary depending on the source. The FundaAI roadmap shared through secondary reporting places Humufish production during Q3 2027 and Triggerfish during Q4 2027, followed by larger volume during 2028. The same reporting estimates broader Google TPU shipments of approximately 10 million to 11 million units during 2027, although that figure may include several TPU products rather than Triggerfish alone.

Kuo offers a more specific estimate for the upgraded design. His industry research suggests Google could order an additional 1 million to 2 million Triggerfish processors across the product lifecycle, on top of an estimated 4 million to 5 million Humufish units. Triggerfish production is expected to begin near the end of 2027 before scaling during 2028, while its more complex design could carry a price approximately 30% higher than Humufish.

The packaging strategy adds another layer to the reported roadmap. Humufish has been linked to Intel’s EMIB T advanced packaging technology, while the primary compute silicon would reportedly continue to be manufactured by TSMC. Under that potential arrangement, MediaTek could contribute I O and backend design work, Intel could provide advanced packaging, and TSMC could continue producing the leading process compute dies.

Google was evaluating Intel EMIB packaging for a future TPU, This remains unconfirmed, but Intel’s own EMIB T technology overview explains why the platform could appeal to AI accelerator designers. Intel says EMIB T localizes dense silicon connections only where they are required, potentially improving substrate utilization, package scalability, and cost efficiency for very large multi die designs with numerous HBM stacks.

This distinction is important because Intel involvement would not necessarily mean the TPU compute dies are fabricated using an Intel process node. Intel could participate as the advanced packaging provider while TSMC continues producing the main silicon. Supply chain constraints could still influence that arrangement, especially as Google, NVIDIA, AMD, and other major customers compete for leading process wafers and advanced packaging capacity.

Google’s reported strategy reflects a wider shift in AI infrastructure. Rather than depending on one universal accelerator, hyperscale companies are building portfolios of custom processors designed for different model stages, cost targets, memory requirements, and latency profiles. Triggerfish appears to push that strategy further by placing more orchestration capability, local memory, and bandwidth inside a single package.

Triggerfish matters because its reported architecture treats AI orchestration as a hardware problem rather than leaving every management task to the external host CPU. Larger SRAM, HBM4E, and a dedicated simulation or management die could keep more agent state and reinforcement learning activity close to the compute engines, reducing the movement that frequently limits real world AI performance.

The project could also represent a major strategic milestone for MediaTek. Successfully contributing to a high volume Google TPU platform would expand its position beyond mobile processors and establish the company as a stronger competitor in custom data center silicon. Broadcom remains deeply established in AI ASIC development, but MediaTek appears to be building a credible alternative around inference, packaging integration, and cost focused design.

Intel may also gain an important opportunity through EMIB T. Even without manufacturing the main compute die, packaging a major Google accelerator would provide valuable external validation for Intel Foundry and establish advanced packaging as a more immediate route into the AI supply chain.

The largest uncertainty is execution. HBM4E availability, packaging yields, thermal limits, supplier coordination, and software optimization will determine whether the reported architecture can move from an ambitious roadmap into a commercially scalable platform. Until Google confirms Triggerfish, it remains an important supply chain signal rather than a finished product announcement.

Could Google’s combination of custom TPUs, HBM4E, and specialized companion dies become a stronger alternative to NVIDIA GPUs for agentic AI infrastructure?