AMD Zen 6 CCD Reportedly Measures 76mm2, Slightly Bigger Than Zen 5 While Packing More Cores
A fresh leak is putting a hard number on AMD Zen 6 chiplet density, and if it holds up, it is a serious signal that the next desktop and server cycle is going to be defined less by raw die growth and more by node enabled packing efficiency. According to a report attributed to HXL, AMD Zen 6 CCD area is expected to land at 76mm2 on TSMC N2, which would be only a modest step up versus recent Zen CCD sizes while delivering a major uplift in core and cache payload.
The key value proposition here is the claimed configuration shift. Zen 6 CCD is described as moving from 8 cores and 32MB L3 in Zen 5 to 12 cores and 48MB L3, a 50% increase in both core count and L3 capacity per CCD. If AMD can deliver that while only expanding CCD area by roughly 5% to 7% versus Zen 4 and Zen 5 class CCDs, it is a strong indicator that TSMC N2 density and AMD floorplan choices are doing real work rather than just marketing work.
Zen2 CCD: 2*4 Core 2*16 MB L3 TSMC N7 ~77 mm2
— HXL (@9550pro) January 30, 2026
Zen3 CCD: 8 Core 32MB L3 TSMC N7 ~83 mm2
Zen4 CCD : 8 Core 32MB L3 TSMC N5 ~72 mm2
Zen5 CCD : 8 Core 32MB L3 TSMC N4 ~71 mm2
Zen6 CCD : 12 Core 48MB L3 TSMC N2 ~76 mm2
The leak also includes a quick historical comparison across CCD generations, showing how AMD has kept chiplet size relatively contained while iterating on the process node and the compute payload.
Zen 2 CCD: 77mm2, 8 cores via 2 clusters of 4, 32MB L3 total, TSMC N7
Zen 3 CCD: 83mm2, 8 cores, 32MB L3, TSMC N7
Zen 4 CCD: 72mm2, 8 cores, 32MB L3, TSMC N5
Zen 5 CCD: 71mm2, 8 cores, 32MB L3, TSMC N4
Zen 6 CCD: 76mm2, 12 cores, 48MB L3, TSMC N2
From a product stack perspective, this rumored CCD profile creates a very clean narrative for AMD across server and client. For servers, higher core density per CCD directly increases the ceiling for total cores per package and makes every chiplet slot more valuable. For desktops, it creates room for higher core count SKUs without requiring a dramatic jump in chiplet area, which can support both performance positioning and manufacturing economics.
The report also echoes earlier chatter that EPYC Venice with Zen 6 CCDs is planned as the first product line built on TSMC N2 nanosheet technology, and that AMD may use N2P broadly across Zen 6 while using an N3P based IOD, with some entry level products potentially staying on N3P. Even if the exact node mix shifts before launch, the operational message remains the same: AMD appears to be building a high density compute roadmap where the CCD carries more of the performance lift, while the broader platform retains a familiar multi chiplet structure.
One more interesting footnote from the same leak stream is a reference to a denser Zen 6C variant, described as roughly 156mm2 while packing 32 cores and 128MB L3 per CCD. If that configuration is real, it reinforces AMD’s likely segmentation play: standard Zen 6 CCDs for higher frequency and client forward tuning, and Zen 6C style CCDs for core heavy throughput markets where density and total cache per socket are a bigger lever.
For gamers and creator workloads, the practical watch items are straightforward. A 12 core CCD can change where AMD draws the product tier lines, how it prices mid to high end SKUs, and how it positions future X3D parts if 3D V Cache moves into a new generation alongside Zen 6. The upside is a clearer path to higher thread counts and more cache without the usual penalty of dramatically larger chiplets. The risk is that real world clocks, thermals, and yield will decide how much of this theoretical density turns into retail volume and reasonable pricing.
If Zen 6 really delivers 12 cores and 48MB L3 per CCD at roughly 76mm2, would you rather see AMD push higher core count desktop CPUs first, or prioritize next generation X3D variants for gaming performance leadership?
