AMD Linux Patches Reveal a New Low Power Core Type Ahead of Zen 6

AMD appears to be preparing a third CPU core classification for future heterogeneous processors, adding a dedicated Low Power category alongside the existing Performance and Efficiency core types already recognized by the Linux kernel.

The development surfaced through a new Linux kernel patch series submitted by AMD engineer Vishal Badole. The series expands the x86 CPU topology system so that Linux can correctly identify AMD processors containing cores specifically optimized for background activity, idle operation, and minimal power consumption.

“This series extends the x86 topology cpu_type classification to support a Low Power core type, in addition to the existing Performance and Efficiency types.”
— Vishal Badole, AMD

AMD heterogeneous processors report their core classifications through CPUID function 0x80000026, which provides extended information about processor topology, efficiency rankings, and core types. The new patch assigns value 2 to the Low Power category, allowing Linux to distinguish it from both conventional Performance cores and denser Efficiency cores. The official Linux kernel topology documentation confirms that this CPUID function can expose core type and power ranking information on heterogeneous AMD processors.

Without the patch, Low Power cores are currently displayed as unknown inside the Linux x86 topology debug interface. The update also changes how these cores calculate their boost ratio, allowing them to use AMD’s reported highest performance value rather than the fixed ceiling normally applied to standard Performance cores. This behavior follows a similar software path to AMD’s existing Efficiency core handling.

The patch itself is small and does not introduce a new Linux scheduler, power management framework, or workload migration policy. Its immediate purpose is to expose the additional core classification correctly so that operating systems and user space software can recognize the hardware and apply appropriate performance scaling behavior.

AMD currently uses standard Zen cores and denser Zen c variants across its product portfolio. Zen c cores retain compatibility with the same fundamental instruction architecture while using a denser physical design intended to improve core density and efficiency, normally at the expense of maximum clock speeds. AMD introduced this approach with Zen 4 and Zen 4c before continuing it with Zen 5 and Zen 5c.

The newly identified Low Power classification appears to represent a separate role. Rather than focusing primarily on fitting more compute cores into a given silicon area, these cores are described as being designed for minimal consumption during idle periods and background workloads. This could allow future AMD mobile processors to keep larger Zen cores inactive during light operating system tasks, notifications, media processing, and other low intensity activity.

The patch does not state that these Low Power cores use the Zen 6 architecture, nor does it identify them as Zen 6LP. It also provides no details regarding cache capacity, clock speeds, silicon area, simultaneous multithreading support, or the exact microarchitecture behind the design. Reports linking the core type directly to Zen 6 and the upcoming Medusa APU family should therefore remain classified as informed speculation rather than confirmed AMD product information.

Previous industry reports have claimed that Medusa Point mobile processors could combine standard Zen 6 cores, dense Zen 6c cores, and a smaller number of dedicated Low Power cores. Early leaks have also suggested that some mobile configurations could use these cores to improve battery life and reduce the need to activate higher performance CPU clusters during light workloads. AMD has not publicly confirmed those configurations.

Software preparation for AMD’s next client architecture is already underway. As previously covered in our AIDA64 Zen 6 support report, AIDA64 v8.30 introduced preliminary support for Zen 6 based APUs. FinalWire did not name Medusa or disclose product configurations, but the update showed that hardware identification work had started before commercial systems reached the market.

AMD has officially confirmed Zen 6 for its next generation EPYC Venice processors, which have entered production ramp using TSMC’s 2 nm process. Our previous report on EPYC Venice production examined AMD’s plans to scale Zen 6 to as many as 256 server cores, demonstrating that the architecture is already advancing toward commercial deployment.

AMD’s desktop Zen 6 roadmap is also expected to introduce substantial platform changes. Recent reporting has connected the Olympic Ridge family with higher core counts, new memory capabilities, and an integrated neural processing unit, although AMD has not confirmed those final specifications. Our Zen 6 desktop roadmap coverage provides further context on the current rumors surrounding AMD’s next Ryzen generation.

The most important part of this Linux patch is not that it confirms a specific Zen 6 product. It confirms that AMD’s hardware topology is becoming more complex than the familiar combination of standard and dense Zen cores.

A dedicated Low Power core could be particularly valuable for notebooks, handheld gaming systems, and compact computers where idle consumption and background efficiency directly affect battery life. Gaming handhelds frequently spend significant time handling operating system services, launchers, downloads, media playback, and suspended applications. Moving those tasks away from larger CPU cores could provide measurable efficiency gains without compromising peak gaming performance.

However, successful implementation will depend heavily on software scheduling. Adding another core tier creates more decisions for Windows, Linux, firmware, and application developers. Workloads must be assigned to the correct cores quickly enough to save power without introducing latency, inconsistent frame pacing, or delayed background processing.

The Linux preparation suggests AMD wants operating system support ready before compatible processors arrive. It does not yet reveal whether the Low Power core will be a reduced Zen 6 design, a modified earlier architecture, or a more specialized implementation. Until AMD publishes architecture documentation, the exact relationship between this new core type, Zen 6, and Medusa remains unconfirmed.

Could dedicated Low Power cores give AMD a meaningful battery life advantage in gaming laptops and handheld systems, or will the added scheduling complexity outweigh the benefits?