AMD EPYC Venice Revealed With 256 Zen 6 Cores and Twin I/O Dies

AMD’s upcoming EPYC Venice processor has appeared in a detailed promotional image at the Moscone Center West in San Francisco ahead of the company’s Advancing AI 2026 keynote. The image provides one of the clearest looks yet at the enormous chiplet layout AMD will use to deliver as many as 256 Zen 6 cores and 512 threads for next generation servers, cloud platforms, high performance computing, and AI infrastructure.

The processor image, first highlighted by ComputerBase, shows 8 large Core Complex Dies positioned around 2 substantial I/O dies. Each compute die appears to contain 32 CPU cores divided between 2 complexes containing 16 cores each. Across all 8 compute dies, the configuration reaches the maximum 256 core count AMD has confirmed for Venice. The promotional image does not reveal the precise functions or manufacturing process used for every visible I/O block, with additional architectural details expected from AMD.

Venice will become AMD’s 6th Gen EPYC platform and will introduce the Zen 6 architecture to the server market. AMD has confirmed that the highest specification models will provide 256 cores and 512 threads, representing a 33.3% increase over the 192 core and 384 thread limit of the current EPYC Turin generation. AMD also says Venice will increase memory bandwidth by approximately 2.5 times compared with EPYC 9005 processors, reaching as much as 1.6 TB/s in supported configurations.

AMD Venice 256 core. pic.twitter.com/hooyKVMwBb

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The processor is also a major manufacturing milestone for AMD and TSMC. AMD announced in May that Venice had entered production ramp using TSMC’s advanced 2 nm technology, describing it as the first high performance computing product in the industry to reach this stage on the process. Initial production is taking place in Taiwan, while AMD also intends to manufacture Venice at TSMC’s Arizona facilities in the future.

TSMC’s N2 process replaces traditional FinFET transistors with gate all around nanosheet transistors. Compared with N3E, TSMC projects that N2 can provide between 10% and 15% higher performance at the same power or between 25% and 30% lower power consumption at the same performance. The company also claims a chip density improvement exceeding 15%, although the gains achieved by Venice will depend on AMD’s architecture, frequencies, power targets, and final product configuration.

AMD previously projected that Venice could deliver up to 1.7 times the performance of its existing server generation. The company has also modeled a 256 core Venice system as delivering approximately 3.30 times the rack level throughput of NVIDIA’s upcoming Vera CPU under a normalized 100 kW rack scenario. These results are AMD projections rather than independent product benchmarks because both Venice and Vera remain future platforms. AMD’s model uses general computing, web serving, Java, database, caching, and other CPU focused workloads associated with large agentic AI environments.

Venice will also form the CPU foundation of AMD’s Helios rack scale AI architecture, working alongside Instinct MI455X accelerators, Pensando networking hardware, and the ROCm software platform. While GPUs remain responsible for large model training and inference, AMD argues that CPUs are becoming increasingly important for agent orchestration, sandbox execution, databases, storage, networking, security, application services, and maintaining data flow across accelerated infrastructure.

EPYC Venice 2 nm production ramp, includ AMD’s plans to use Zen 6 and higher core density to compete across enterprise servers, cloud computing, and agentic AI deployments. The newly revealed package image now provides a clearer indication of the physical scale required to place 256 CPU cores and 2 large I/O dies into a single EPYC processor.

EPYC Venice demonstrates that the next stage of AI infrastructure will not be defined by accelerators alone. Agentic systems create continuous demand for databases, application servers, tool execution, networking, storage, security, and orchestration, making CPU density an increasingly important part of rack design.

The 256 core configuration gives AMD a substantial density advantage on paper, but the decisive metrics will be sustained performance, memory behavior, power consumption, platform cost, and software deployment at scale. AMD’s comparisons against NVIDIA Vera are strategically important, although independent testing will be required before any performance leadership can be confirmed.

Will AMD’s 256 core EPYC Venice give the company a decisive advantage in AI infrastructure, or can NVIDIA Vera and Intel’s future Xeon platforms close the gap?