SMIC Plans to Strengthen Cooperation With OSAT Partners to Accelerate Advanced Packaging Development
Advanced packaging has become one of the most strategic levers in modern semiconductors, especially as scaling gains are no longer driven only by shrinking transistors. Instead, the industry is increasingly relying on backend innovation, where stacking, interconnect density, and packaging architecture can unlock meaningful performance and efficiency uplifts for demanding workloads. TSMC CoWoS is the most obvious example of how backend execution can become a competitive moat, and now it appears SMIC wants to move more aggressively in that same direction.
According to a DigiTimes report, SMIC is exploring advanced packaging by establishing a dedicated research organization in Shanghai, focused on developing key technologies and improving integration between wafer manufacturing and packaging and testing operations. The report frames this initiative as a way to strengthen coordination across the backend supply chain and build a clearer pathway for SMIC to pursue packaging focused scaling approaches.
This move is not coming out of nowhere. SMIC has previously been linked to cooperation efforts in packaging, including reported joint venture activity with JCET Group, but the capabilities commonly associated with SMIC aligned packaging have not been positioned as a direct peer to the leading 2.5D and 3D solutions used for high performance computing scale products. Instead, prior coverage has tended to place SMIC adjacent efforts around more established packaging and testing services such as wafer bumping, wafer level packaging, chip scale packaging, conventional packages, and testing.
The key takeaway from the new DigiTimes reporting is the intent signal. SMIC appears to be prioritizing tighter alignment between its wafer side operations and its packaging and test side execution, which strongly suggests deeper reliance on OSAT partners in the near term, while building internal capability through research and process development. That matters because advanced packaging is not something a foundry can spin up quickly. The ecosystem requires ultra high precision tools, advanced substrates and interposers, mature bonding processes, and a validated supply chain that can deliver consistent yields at scale. Even for leading players, packaging capacity has become a bottleneck that constrains shipments.
In the broader market, the strategic logic is straightforward. Demand for advanced packaging remains elevated because the advantages are too compelling for high performance applications, especially where compute density and memory bandwidth dominate the performance equation. China’s semiconductor roadmap is facing constraints around leading edge transistor scaling, and while advanced packaging cannot fully replace node leadership, it can create a meaningful performance bridge for certain classes of products, particularly when combined with design optimization and system level integration.
If SMIC can strengthen packaging coordination and partner execution effectively, it could improve the competitiveness of Chinese silicon programs that are currently limited by process technology access. The realistic expectation is that results will be incremental rather than immediate, but as the industry shifts toward packaging driven scaling, this is the kind of investment foundries can no longer afford to ignore.
Do you think advanced packaging can meaningfully narrow the performance gap for China’s chip ecosystem, or is leading edge process technology still the only factor that truly matters for high performance computing?
