Second Gen 3Gb A-Die Memory Spotted on Facebook, May Feature Native JEDEC Speed of 7200 MT/s
A new generation of SK Hynix DDR5 DRAM appears to be on the way after photos of what seems to be the second-generation 3Gb A-die memory chip surfaced in the Facebook group Clock’EM UP, posted by Kevin Wu from Team Group. The IC, labeled X021 with the part code AKBD, was later analyzed by hardware insider @unikoshardware, who confirmed that the X021 marking identifies it as a second-generation 3Gb A-die, designed to succeed the 3Gb M-die used in current DDR5 modules.
new hynix ddr5
— UNIKO's Hardware 🌏 (@unikoshardware) October 21, 2025
judging by x021, it should be the 3gb dies.
so the second gen of 3gb hynix dies has arrived, after the first gen 3gb m die.
and the native speed is also brand new, AKBD
a=adie
KB=???? speed
given eb=4800, gb=5600, hb=6400,
i gues kb is likely to be 7200 or even… pic.twitter.com/gKhPre8MMT
While SK Hynix has not made any official announcement yet, the leaked image provides several hints about its specifications. Based on SK Hynix’s established naming convention, letter pairs such as EB, GB, and HB have corresponded to 4800, 5600, and 6400 MT/s JEDEC speeds. Therefore, the new KB designation likely points to a native 7200 MT/s JEDEC speed, which Kevin Wu also confirmed in his comments on the post.
If the speculation proves accurate, this development aligns with Intel’s upcoming Arrow Lake Refresh and Panther Lake platforms, which are expected to officially support DDR5-7200 speeds under Intel’s Plan of Record. This marks a notable jump from Raptor Lake’s DDR5-5600 and Arrow Lake’s DDR5-6400, suggesting that the new A-die AKBD chips will serve as the foundation for the next generation of high-frequency DDR5 kits aimed at enthusiasts and system builders alike.
One observation from the leaked sample is that it appears to use an 8-layer PCB, which could influence its stability at higher frequencies. In most cases, 8-layer PCBs face challenges maintaining signal integrity and power delivery at speeds beyond 8000 MT/s, even with advanced ICs such as A-die.
To unlock the chip’s full potential, manufacturers typically employ 10-layer or 12-layer PCBs, which offer cleaner signal paths and improved power efficiency. These designs are essential for achieving the extreme frequencies that many enthusiasts have already reached with earlier DDR5 generations, including 10,000 MT/s and beyond. As a result, memory makers will likely pair the new AKBD chips with higher-layer PCBs to ensure performance stability and achieve the speeds enthusiasts expect from next-generation DDR5.
| Specification | Details |
|---|---|
| Die Type | SK Hynix 3Gb A-Die (2nd Generation) |
| Marking | X021 |
| Part Code | AKBD |
| Native Speed (Speculated) | 7200 MT/s (JEDEC) |
| Platform Compatibility | Intel Arrow Lake Refresh, Panther Lake |
| PCB Type (Sample) | 8-Layer PCB |
| Potential Limitation | Signal integrity above 8000 MT/s on 8-layer PCBs |
This second-generation 3Gb A-die may mark another leap in DRAM performance, positioning SK Hynix to lead the next phase of DDR5 memory technology. With support for faster JEDEC standards and improved overclocking potential, these new chips could become the cornerstone of 2026’s high-end memory modules.
Do you think DDR5-7200 JEDEC will become the new baseline next year, or will overclockers continue to chase 10,000 MT/s and beyond? Share your thoughts below.
