Cerebras Maps CS-5 and CS-6 Roadmap After CS-4 Pushes AI Inference Up to 30x Faster

Cerebras has revealed an aggressive roadmap extending beyond its newly announced CS-4, with CS-5 targeted for 2027 and CS-6 planned to take wafer scale computing into 3D memory integration. During Hot Chips 2026, Cerebras detailed how its new Nexus rack architecture is intended to support several generations of Wafer Scale Engines while pushing token generation speed higher every year. CS-4 is already entering shipment this quarter, but the more ambitious targets include as much as 10,000 output tokens per second per user with CS-5 and dramatically larger integrated memory capacity through CS-6.

CS-4 establishes the foundation for that roadmap using 3 WSE 3 Turbo processors inside a single Nexus rack. Each wafer contains 4 trillion transistors, 900,000 AI optimized cores and 44 GB of integrated SRAM while delivering up to 250 PFLOPS of AI compute and 43.2 PB/s of memory bandwidth. Across the complete rack, Cerebras reaches 750 PFLOPS, 129.6 PB/s of memory bandwidth, 160.5 PB/s of on chip fabric bandwidth and 7.2 Tb/s of external I O bandwidth. Communication latency between connected wafers can fall as low as 2 microseconds.

Cerebras claims CS-4 can reach more than 4,400 tokens per second per user on GPT OSS 120B, with inference performance reaching up to 30x the GPU systems used in its comparison. The company also claims up to 2x the inference speed of CS-3 and as much as 10x higher throughput per watt. Those figures combine third party Artificial Analysis data with internal Cerebras benchmarking, meaning actual performance will vary according to model architecture, context length, serving configuration and concurrency. Earlier coverage of Cerebras CS-4 explored how the WSE 3 Turbo achieves those gains through enormous SRAM bandwidth and a redesigned rack architecture rather than moving to a smaller manufacturing process.

The Nexus platform is designed so Cerebras can upgrade compute, power, cooling and I O independently. Each wafer is contained inside a removable compute backpack with its own power conversion, liquid cooling and connectivity. Cerebras places power conversion around 0.5 mm from the processor, compared with roughly 50 mm in conventional GPU board designs, which the company says reduces electrical losses and allows significantly more power to reach the wafer. The modular approach also reduces component count by 50% compared with the previous generation and uses 60% more automated manufacturing.

CS-5 is where the roadmap becomes more aggressive. Targeted for 2027, the next system will combine Nexus with a new generation Wafer Scale Engine and is designed to deliver up to 10,000 output tokens per second per user on models including Gemma 4 31B and GPT OSS 120B. For much larger frontier models such as Kimi and GPT 5.6 Sol, Cerebras is targeting up to 5,000 output tokens per second per user and approximately 3 million tokens per second per megawatt. The architecture is also being designed to support models exceeding 50 trillion parameters while maintaining interactive inference speeds. These remain forward looking performance targets rather than shipping benchmark results.

That focus directly targets agentic AI, where a single user request can trigger many sequential model calls, verification steps and tool interactions. Increasing token generation from hundreds to thousands of tokens per second could reduce the total time required for complex coding, research and reasoning workloads. Cerebras hardware is already being used for latency sensitive inference workloads, with OpenAI researchers previously highlighting the speed of models running on Cerebras systems as the company expands its partnership with AMD Helios and other heterogeneous AI infrastructure.

CS-6 takes the architecture in a different direction by moving wafer scale computing into the third dimension. Cerebras says development began in 2024 and plans to integrate wafer scale SRAM and compute with 3D stacked DRAM through ultra high bandwidth connections. Since the Wafer Scale Engine already occupies effectively the maximum practical area available in 2 dimensions, adding memory vertically becomes the next major scaling opportunity. The goal is to place far more of a model close to the compute hardware without sacrificing the low latency data locality that gives Cerebras its inference advantage.

Cerebras expects the additional memory to reduce the number of systems needed to run very large models, potentially delivering similar or greater capability from an order of magnitude smaller infrastructure footprint. The company has not announced a commercial launch date, final specifications or production configuration for CS-6, making it a longer term architectural roadmap rather than a product approaching immediate deployment.

CS-4 is already unusual because Cerebras is not trying to beat NVIDIA by building another GPU. It is attacking one of AI inference's biggest bottlenecks by putting enormous compute, SRAM and communication bandwidth onto wafer scale silicon. CS-5 and CS-6 show that the company believes this advantage can compound rather than disappear as conventional accelerators become faster.

The 10,000 tokens per second target for CS-5 could be transformative for agentic workloads if Cerebras can deliver it under realistic production conditions. CS-6 may be even more important because 3D integrated memory addresses the next obvious limitation of wafer scale computing. The biggest challenge will be turning these architectural targets into reliable, economical systems at hyperscale. NVIDIA, AMD, Groq and custom ASIC developers are all moving quickly, so Cerebras will need more than headline token speed. It will need software compatibility, deployment scale and strong economics to convert wafer scale performance into lasting market share.

Would 10,000 tokens per second fundamentally change how you use AI agents, or are model intelligence and reliability still more important than raw inference speed?