Intel Unveils Clearwater Forest Xeon CPUs With 288 Darkmont E-Cores, 18A Process, and DDR5-8000 Support

At Hot Chips 2025, Intel revealed one of its most ambitious server CPU architectures to date: Clearwater Forest, the company’s first E-Core only Xeon family to be built on the 18A process node. These new chips scale up to an impressive 288 efficiency cores distributed across 12 chiplets and introduce substantial architectural enhancements aimed at boosting performance, efficiency, and scalability for dense data center workloads.

Clearwater Forest in Intel’s Roadmap: The E-Core Counterpart to Diamond Rapids

Intel’s Xeon roadmap continues to divide into performance-core (P-Core) and efficiency-core (E-Core) product lines. While the upcoming Diamond Rapids CPUs will target traditional compute-intensive and AI-heavy workloads with P-Cores, Clearwater Forest is built exclusively with E-Cores, optimized for high-density, scale-out environments where efficiency and raw thread count matter more than maximum single-thread performance. This mirrors the approach Intel used with Granite Rapids and Sierra Forest under the Xeon 6 banner but pushes the concept significantly further.

Manufactured on Intel’s 18A Process

Clearwater Forest represents the first Xeon family to take advantage of Intel’s 18A manufacturing process, the same node that will underpin the upcoming Panther Lake client CPUs. 18A introduces several critical improvements:

• Backside Power Delivery (PowerVia): Improves efficiency by reducing power loss by up to 5%.

• Gate-All-Around RibbonFET transistors: Deliver reduced gate capacitance and higher density.

• 90% cell utilization: Allowing higher effective density and better signal routing.

• Improved RC delay characteristics: Helping cores communicate more efficiently and scale without excessive power draw.

These innovations give Clearwater Forest a stronger efficiency profile compared to earlier Xeon generations, particularly Sierra Forest, which was limited to the Intel 3 node.

Darkmont E-Cores: Architectural Improvements Over Sierra Glen

Clearwater Forest uses Intel’s new Darkmont E-Cores, a significant step forward from the Sierra Glen cores used in Sierra Forest. Key improvements include:

• Front-End Enhancements:

  • 64 KB instruction cache.

  • Triple 3-wide decoders delivering 9 decodes per cycle (+50% bandwidth).

  • A more accurate branch predictor, likely with deeper history tables and larger structures.

• Out-of-Order Execution (OOE) Engine:

  • 8-wide allocation (+60%).

  • 16-wide retire (2x improvement).

  • Out-of-order window increased to 416 entries (+60%).

• Execution Engine:

  • 26 execution ports (+50%).

  • Integer and vector units doubled.

  • Load AGUs up by 1.5x, Store AGUs doubled.

  • Deeper buffers with 128 outstanding L2 misses (+2x).

• Memory Subsystem:

  • Smarter prefetchers.

  • Triple-load issue capability.

  • ECC protection on L1 Data.

Intel claims these changes result in a 17% IPC uplift compared to Sierra Glen, measured in SpecIntRate’17 benchmarks.

Modular Chiplet Architecture

Clearwater Forest embraces a chiplet-based design with Intel’s advanced packaging technologies. The CPU package consists of:

• 12 E-Core chiplets built on Intel 18A, housing up to 288 Darkmont cores.

• 3 base tiles on Intel 3, containing fabric, last-level cache (LLC), memory controllers, and I/O.

• 2 I/O chiplets built on Intel 7, featuring PCIe, CXL, and accelerators.

These components are connected using Intel’s EMIB interconnect and Foveros Direct 3D stacking, enabling short, high-density interconnects with better efficiency and bandwidth.

The coherent mesh fabric supports shorter signal routes, more metal resources, and improved interconnect density, boosting performance-per-watt while allowing the architecture to scale to extremely high core counts.

Cache and Memory Subsystem

Each cluster of four Darkmont cores shares a 4 MB unified L2 cache with 17-cycle latency. Across a 288-core configuration, that totals 288 MB of L2 cache. Bandwidth is doubled compared to Sierra Forest, offering up to 400 GB/s per cluster.

The LLC is also significantly expanded, reaching up to 576 MB, enabling larger datasets to be handled more efficiently within the chip itself.

Memory support also takes a leap forward:

• 12-channel DDR5-8000.

• Up to 3 TB per socket.

• Memory bandwidth up to 1300 GB/s in 2-socket (2S) configurations, a substantial increase over Sierra Forest’s DDR5-6400 maximum.

Platform I/O and Scalability

Clearwater Forest supports a wide range of next-gen connectivity standards:

• 2 × 96 PCIe Gen5 lanes.

• 64 CXL lanes for advanced memory pooling and accelerators.

• 144 UPI lanes delivering 576 GB/s inter-socket bandwidth.

In dual-socket configurations, the platform can scale to:

• 576 E-Cores.

• 1152 MB LLC.

• ~59 TF/s throughput.

• 5000 GB/s aggregate fabric bandwidth.

This positions Clearwater Forest as one of the most powerful high-density CPUs Intel has ever designed, clearly targeting hyperscalers, cloud providers, and large-scale data center operators.

Data Center Features and Reliability

Beyond raw performance, Clearwater Forest incorporates advanced RASM (Reliability, Availability, Serviceability, Manageability) features critical for enterprise deployments:

• ECC support across L1/L2.

• Data poisoning recovery.

• Local and recoverable machine check support.

• Lockstep operation for mission-critical environments.

• 52-bit physical address space for larger memory addressing.

Intel’s Vision for Clearwater Forest

By building Clearwater Forest entirely on E-Cores, Intel is clearly positioning it as the scale-out efficiency leader in its Xeon portfolio. With its 18A foundation, high-bandwidth cache and memory, and extreme scalability up to 576 cores in a dual-socket configuration, it aims to directly compete with AMD’s EPYC Bergamo (128 Zen 4c cores) and future ARM-based hyperscaler solutions.

Availability

Intel confirmed that Clearwater Forest Xeon CPUs will launch in upcoming quarters, with broader production expected to ramp in late 2025 to early 2026. It will debut alongside Diamond Rapids (P-Cores), ensuring that Intel can address both ends of the performance-density spectrum in next-generation data centers.

Do you think Intel’s 288-core Clearwater Forest will be enough to regain ground against AMD’s EPYC and ARM’s growing server dominance, or is it too late for Intel in hyperscale markets?